1. Field of the Invention
The present invention generally relates to a memory structure and fabricating method thereof, more particularly, to a flash memory structure and fabricating method thereof.
2. Description of Related Art
Flash memory device is a type of non-volatile memory that allows multiple data writing, reading and erasing operations. Furthermore, the stored data will be retained even after power to the device is removed. With these advantages, flash memory has been broadly applied in personal computer and electronic equipment.
A typical flash memory device has a floating gate and a control gate fabricated using doped polysilicon. Moreover, the control gate is directly disposed on the floating gate. The floating gate is isolated from the control gate by an inter-gate dielectric layer and the floating gate is isolated from the substrate by a tunnel oxide layer (that is, the so-called stack gate flash memory).
FIG. 1 is a schematic cross-sectional view of a conventional stack gate flash memory structure.
In the stack gate flash memory shown in FIG. 1, the stack gate structure 102 on the substrate 100 includes a tunnel oxide layer 104, a floating gate 106, an inter-gate dielectric layer 108 and a control gate 110. The source region 112 and the drain region 114 are disposed in the substrate 100 on each side of the stack gate structure 102. Furthermore, the contact window 118 in the dielectric layer 116 connects the drain region 114 and the conducting line 120.
As integrated circuits are aiming toward a higher level of integration through miniaturization, the dimension of each memory cell in a flash memory device must be reduced in order to increase the integration of memory devices. The miniaturization of memory cell can be achieved through a reduction of the gate length of a memory cell and a reduction of the isolating partition between data lines. However, reducing the gate length will shorten the channel length under the tunnel oxide layer 104 and can easily lead to abnormal punch through between the source region 112 and the drain region 114. Therefore, electrical performance of the memory cell can be adversely affected.
On the other hand, the larger the gate coupling rate (GCR) between the control gate 110 and the floating gate 106, the lower operating voltage required to operate the memory so that the memory can have a higher performance. However, in a conventional stack gate flash memory, two adjacent floating gates 106 are isolated from each other through the dielectric layer 116. Since adjacent floating gates 106 are coupled, induced capacitance will be generated. As a result, the GCR of the flash memory is reduced and the performance of the flash memory is compromised.